In recent years, regarding large-scale semiconductor integrated circuit devices (LSIs), micronization (size reduction) of circuit elements is being advanced in order to enhance the operating speed further and reduce the area of a chip. For example, when an LSI is constructed using MOS devices, the thickness of a gate oxide film becomes thinner with micronization of circuit elements. Therefore, it becomes necessary to lower a gate application voltage in order to secure a sufficient element life, and also to prevent an excessive voltage from being applied to the element in order to avoid breakdown of the element.
For element life, it is effective to reduce the power supply voltage using a step-down circuit. This measure is mainly used in inside logic circuits of the LSI. For excessive voltages, it is effective to add a clamp circuit to a, buffer circuit or interface circuit provided between an external signal input terminal and the internal circuit or to add a clamp circuit outside the LSI. Such a clamp circuit is proposed in U.S. Pat. No. 6,737,905 (JP 2003-258581A).
According to this clamp circuit, external parts of an integrated circuit device become unnecessary except for a current limiting resistor etc., and consequently the area of a substrate can be reduced and the cost can be curtailed. Moreover, an input voltage detection circuit and a reference voltage generator circuit can set a clamp starting voltage to a desired value by properly setting structures of resistor circuits. In addition, these circuits have an advantage that the clamp starting voltage is resistant to fluctuate etc.
This clamp circuit is constructed so that an offset voltage for setting the clamp starting voltage is determined by a relationship among transistors of source follower connection and resistors. However, with a structure like this, the clamp starting voltage is resistant to fluctuate, the circuit cannot avoid being affected from variations in constants of the source follower transistors and the resistors, and hence there is a limit in controlling the clamp starting voltage accurately.
As another countermeasure to excessive input voltages, an input interface circuit of a semiconductor integrated circuit device is proposed in U.S. Pat. No. 6,653,884 (JP 2002-43924A). FIG. 5 shows a structure of this interface circuit. A signal transferred to an input terminal (external input terminal) 113 of a microcomputer (semiconductor integrated circuit device) 111 from the outside is transferred to an input terminal (internal input terminal) 115 of an inverter 114 that constitutes an internal circuit of the microcomputer 111. Between the power supply VCC and the input terminal 115, a series circuit of P-channel MOSFETs (first and second P-MOSFETs) 116 and 117 is connected. Between the input terminal 115 and the ground, a series circuit of N-channel MOSFETs (first and second N-MOSFETs) 118 and 119 is connected.
On the other hand, between the power supply VCC and the input terminal 113, a series circuit of a P-channel MOSFET 120 (fourth P-MOSFET) and a P-channel MOSFET 121 (third P-MOSFET) is connected; between the input terminal 113 and the ground, a series circuit of an N-channel MOSFET 122 (third N-MOSFET) and an N-channel MOSFET (fourth N-MOSFET) 123 is connected.
Moreover, between the power supply VCC and the input terminal 113, a parasitic diode 124 formed in the semiconductor substrate in connection with formation of FETs 120 and 121 is connected. Between the input terminal 113 and the ground, a parasitic diode 125 formed in the semiconductor substrate in connection with formation of FETs 122 and 123 is connected. A high-level signal is always provided to a gate of the FET 120, and a low-level signal is always provided to a gate of the FET 123. This is adopted when each gate is used as an input interface.
A gate of the FET 116 is connected to a common junction point of the FETs 120 and 121, and a gate of the FET 119 is connected to the common junction point of the FETs 122 and 123. The voltage of the power supply VCC is 5V, and the intermediate potential 3V is applied to gates of the FETs 117, 118, 121 and 122. This intermediate potential 3V is generated from the power supply VCC as a power supply for operating the microcomputer 111 in the case where a core part of the microcomputer 111 is constructed to operate at 3V (actually, 3.3V).
A source of a P-channel MOSFET (fifth P-MOSFET, MOSFET for protection) 129 is connected to a common junction point of the FETs 116 and 117 along with its gate, and a drain of the FET 129 is connected to the gate of the FET 117. A source of an N-channel MOSFET (fifth N-MOSFET, MOSFET for protection) 130 is connected to a common junction point of the FETs 118 and 119 along with its gate, and a drain of the FET 130 is connected to the gate of the FET 118.
The drain of a P-channel MOSFET (sixth P-MOSFET, MOSFET for protection) 131 is connected to a common junction point of the FETs 120 and 121 along with its gate, and a source of the FET 131 is connected to a gate of the FET 121. A drain of an N-channel MOSFET (sixth N-MOSFET, MOSFET for protection) 132 is connected to a common junction point of the FETs 122 and 123 along with its gate, and a source of the FET 132 is connected to a gate of the FET 122. The above structure constitutes an input interface circuit 133.
According to the above input interface circuit 133, even when a high voltage of positive polarity or negative polarity is applied to the input terminal 113, a voltage higher than the power supply voltage 5V is not applied on gate oxide films of the FETs. Consequently, the input interface circuit 133 eliminates the need for a process to form a thick gate oxide film that makes a part of the FETs structurally high-voltage resistive, which makes possible to eliminate a manufacturing process and reduce the cost.
Moreover, in case the potential of the line path that has high impedance when both of the two FETs connected in series are turned off, the input interface circuit can prevent each FET from being destroyed. This interface circuit 133 is applied to a semiconductor integrated circuit (IC) mounted on a vehicle.
For example, as shown in FIG. 6, the following case is considered. The operating power supply voltage VCC of an IC is 5V, and the input interface circuit 133 is applied to the multi-purpose input terminal 113 that is connected to the battery voltage +B of 12V through a resistor. FIG. 6 shows only an input side of the input interface circuit 133 and clearly illustrates a circuit part that generates and impresses an intermediate potential of 3V.
A reference voltage generation circuit 134 generates a reference voltage based on the power supply VCC, and outputs it to the non-inverting input terminal of an operational amplifier 135. Between the power supply VCC and the ground, a series circuit of a P-MOSFET 136 and resistors 137a, 138 is connected. A common junction point of the resistors 137a, 138 is connected to the inverting input terminal of the operational amplifier 135, and the output terminal of the operational amplifier 135 is connected to a gate of the FET 136. The above structure constitutes a voltage generation circuit 137 that is a series regulator. An intermediate potential of 3V is supplied from a drain of the FET 136.
The intermediate potential (intermediate voltage) VDD generated by the voltage generation circuit 137 is applied through intermediate voltage application switch units 139 and 140. The switch unit 139 on the power supply side includes an N-MOSFET 141 and a P-MOSFET 142 with their output-side terminals mutually connected. One of them is connected to the output terminal of the voltage generation circuit 137, and the other is connected the gate of the FET 121. Moreover, the gate of the FET 121 is connected to the ground through an N-MOSFET 143, and a gate of the FET 143 is connected with a gate of the FET 142 in common. The output enable signal OE is provided to the gates of the FETs 142 and 143, and its inverted signal OE_N is provided to a gate of the FET 141.
On the other hand, the switch unit 140 on the ground side includes an N-MOSFET 144 and a P-MOSFET 145 with their output-side terminals mutually connected. One of them is connected to the voltage generation circuit 137 and the other is connected to the gate of the FET 122. Moreover, the gate of the FET 122 is connected to the power supply VCC through a P-MOSFET 146, and a gate of the FET 146 is connected with a gate of the FET 144 in common. The enable signal OE is provided to a gate of the FET 145, and its inverted signal OE_N is provided to the gates of the FETs 144 and 146.
That is, when the input terminal 113 is used as an input port, the enable signal OE is made to take a low level. At this time, the FET 142 is turned on in the switch unit 139 on the power supply side, and consequently the intermediate voltage VDD is applied to the gate of the FET 121. Then, in the switch unit 140 on the ground side, the FET 145 is turned on, and consequently the intermediate voltage VDD is also applied to the gate of the FET 122.
On the other hand, when the input terminal 113 is used as an output port, the enable signal OE is made to take a high level. At this time, in the switch unit 139 on the power supply side, both of the FETs 141 and 142 are turned off and the FET 143 is turned on. Consequently the gate of the FET 121 is set to the ground potential. Moreover, also in the switch unit 140 on the ground side, both of the FETs 144 and 145 are turned off and the FET 146 is turned on. Consequently the gate of the FET 122 is set to the power supply voltage VCC.
The intermediate voltage VDD generated and outputted by the voltage generation circuit 137 is supplied to the switch units 139 and 140 through the output terminal VDD_OUT, an external wiring pattern 147, and an input terminal VDD_IN. This is to allow a bypass capacitor 148 to be externally attached to the power supply wiring of the voltage VDD.
Moreover, the reason of separation of the output terminal VDD_OUT and the input terminal VDD_IN is that the external wiring pattern 147 is extended so that the noise eliminating capacitor 148 of a relatively large capacitance is connected in a path in which the power supply current flows, which allows the capacitor 148 to exert its noise eliminating action more effectively. Therefore, for some ICs that do not need these measures, it is not necessary to take out the intermediate voltage VDD to the outside.
To prevent the capacity of a battery from being exhausted (battery run-out), it is turned out that the above input interface circuit involves the following problem. The input terminal 113 is connected to the battery power supply +B through a resistor 149. In this case, a current depending on the terminal voltage of the resistor 149 flows in the microcomputer 111. Conventionally, this did not become a problem since the amount of current flowing in through the resistor 149 was below a consumed electric current at the time of low consumption power mode (sleep mode, stop mode, etc.) in which the microcomputer 111 was in a standby state.
However, since lower consumed electric current at the time of standby of the microcomputer 111 has been attained, there arises a case where the amount of current flowing in through the resistor 149 exceeds the consumed electric current of the microcomputer 111. In this case, since a source of the FET 120 is connected to the power supply VCC and its gate potential is also at a high level (=VCC), the drain potential, i.e., a source potential of the FET 131, becomes [VCC+VF].
FIG. 7 shows a structure of the FET 131 when formed with semiconductors. An N-well 152 is formed on a P-type semiconductor substrate 151, and a P-type source region 153 and a drain region 154 are formed in the N-well 152. A gate electrode 155 is made of polysilicon. Since the substrate potential (back gate) of the N-well 152 is VCC, a parasitic PNP transistor 156 formed with a source region 153 (P), the N-well 152 (N), and a drain region 154 (P) is turned on.
At this time, a path through which a current flows into the drain side of the FET 131, i.e., a supply side of the intermediate voltage VDD, is formed, but a path through which the current is sunk on the ground side does not exist. As a result, it is likely that the intermediate voltage VDD may be raised and even the power supply voltage VCC may be raised. Conventionally, to cope with such a phenomenon, a resistor 157 (shown by a broken line) corresponding to the amount of the injected current is attached externally to the supply terminal of the intermediate voltage VDD, and the resistor 157 consumes the current so that increase in the power supply voltage VCC is prevented.
However, in this measure, it is necessary to determine the resistor value in order to keep the power supply voltage VCC at a prescribed voltage and select the resistor examining its temperature characteristic, manufacture variation, etc. Further, a Zener diode etc. is also necessary for prevention of breakdown of the microcomputer 111, and consequently this measure becomes a cost factor.